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Extra resources for IA-32 Intel Architecture Software Developer’s Manual. System Programming Guide

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3. SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER The system flags and IOPL field of the EFLAGS register control I/O, maskable hardware interrupts, debugging, task switching, and the virtual-8086 mode (see Figure 2-3). Only privileged code (typically operating system or executive code) should be allowed to modify these bits. 2-7 SYSTEM ARCHITECTURE OVERVIEW The functions of the system flags and IOPL are as follows: TF Trap (bit 8). Set to enable single-step mode for debugging; clear to disable single-step mode.

ABOUT THIS MANUAL NOTE Avoid any software dependence upon the state of reserved bits in IA-32 registers. Depending upon the values of reserved register bits will make software dependent upon the unspecified manner in which the processor handles these bits. Programs that depend upon reserved values risk incompatibility with future processors. Highest 31 Address Data Structure 8 7 24 23 16 15 Byte 3 Byte 2 Byte 1 Bit offset 0 Byte 0 28 24 20 16 12 8 4 0 Lowest Address Byte Offset Figure 1-1. 3. Instruction Operands When instructions are represented symbolically, a subset of the IA-32 assembly language is used.

The base address and limit in the register can then be changed as part of the processor initialization process. , “Interrupt Descriptor Table (IDT)”, for more information on the base address and limit fields. 4. Task Register (TR) The task register holds the 16-bit segment selector, 32-bit base address, 16-bit segment limit, and descriptor attributes for the TSS of the current task. It references a TSS descriptor in the GDT. The base address specifies the linear address of byte 0 of the TSS; the segment limit specifies the number of bytes in the TSS.

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